1. Field of the Invention
This invention relates generally to semiconductor-based programmable memory arrays. Specifically, it relates to programmable memory arrays using laser programmable links.
2. Prior Art
Programmable read only memory (PROM), programmable logic arrays (PLA), and other forms of programmable logic devices (PLD) are available in many different forms, but all such arrays are based upon silicon semiconductor technology. While compound semiconductor-based (i.e., for example, gallium arsenide-based) integrated circuits have taken longer to develop, gallium arsenide (GaAs) based logic and memory integrated circuits are commercially available. However, limitations of compound semiconductor technology have prevented the development of semiconductor PROMs, PLAs and PLDs in that technology even though the performance of such devices would be significantly enhanced by its use.
To better understand the limitations of using the silicon-based PROM and PLA technology, consider a typical field programmable silicon memory array as shown in FIG. 1. There are N parallel word lines 10 arranged in rows and M parallel bit lines 11 orthogonal to the word lines. A fuse 12 and diode 13 in series connect each intersection of a word and a bit line, while a resistive load 14 typically connects one end of each bit line to ground. To program the array means are provided to select a desired word line and a desired bit line, and then a current sufficient to blow the fuse connecting the two lines is passed through the fuse-diode combination. The programmer can configure the array in any desired fashion by eliminating the interconnections between the bit and word lines. Many compound semiconductor-based devices and even some silicon-based devices cannot support the current or voltage necessary to blow the fuse. Hence, a PROM, a PLA or a PLD based upon electrically blown fuses can be implemented with present technology effectively in only a narrow group of silicon semiconductors. Further, even in the group of silicon-based semiconductor devices which can support the voltage and current necessary to blow the fuse, when the array size becomes large the loss of voltage and current in the programming conductive path can cause inadequate programming in some portions of the array circuit.
The electrically blown fuse fabrication of a silicon-based device requires multiple steps which must be carefully controlled. As shown in FIG. 2a, first the fuse material 27 is deposited on the substrate 26. The thickness of the fuse material must be carefully controlled to assure proper operation in the programming mode. Next, a metallization layer 28 is deposited over the fuse material and then the metallization layer is etched away to expose the fuse as shown in FIG. 2b. Each of these steps must be carefully performed or the fuse connection will not function correctly during the programming operation.
A field programmable silicon-based PLA or PROM, as in FIG. 1, gives the programmer flexibility in obtaining a desired circuit, but the performance of such a device is compromised because large voltage and current is required to program the array, and the programming circuit often represents a significant portion of the entire memory chip thereby dissipating more power and consuming large chip area. The components comprising the programmable array, which are fabricated to withstand the large programming voltage, perform slower than components which are not fabricated to withstand such voltages Hence, the speed of a field programmable silicon-based PLA or PROM is degraded by the requirement that the device withstand the large programming voltage. The requirement that the circuit withstand a large voltage also constrains the circuit design Furthermore, the layout of a circuit which must withstand high voltages is larger than that of a circuit which does not need to withstand large voltages. The larger layout reduces the speed of the device and decreases the yield.
The programming circuit for a PLA or PROM not only represents a significant portion of the entire memory chip, but also the programming circuitry degrades the performance of the device. Although the programming circuitry is not needed after the programming of the chip, it remains connected to the memory array after programming and the programming circuitry acts as an additional load on the array during normal operation. This additional load reduces the performance of the array, specifically the speed of the array.
Several different approaches have been tried to enhance both the performance of silicon-based PROMs and PLAs and the reliability of programming large arrays. For example, Chua, "Programmable Write-Once, Read-Only Semiconductor Memory Array Using SCR Current Sink and Current Sources Devices", U.S. Pat. No. 4,130,889 issued Dec. 19, 1978, adds additional circuitry at the end of each word and bit line in the array to enhance the performance of the array. While this invention may make large arrays feasible and while it may increase the reliable performance of a large array, it and the other approaches cannot eliminate the problems in performance introduced by the requirements of a large programming voltage and current.
In the prior art, other approaches have been used to program semiconductor devices. For example, in the desire to provide flexibility to the user of gate arrays, a silicon-based device having various gate arrays interconnected by laser programmable links, i.e. links which may be blown with a laser, has been developed (see Laserpath Applications Note AN-1 dated June 1986 and entitled "One Day Laser Programmed Gate Arrays"). This device is a large silicon-based circuit comprised of transistors which are interconnected with laser programmable links and various groups of these transistors are further interconnected with laser programmable links. To program the circuit, the links connecting the transistors are blown so that the transistors form a desired gate. Then, the programmable links connecting the group of transistors comprising the gate with other groups of transistors comprising other gates are blown to provide the user-specified gate interconnections. The various combinations of transistors to form gates and combinations of gates to form a gate array circuit requires a large number of programmable links and a large circuit.
While the large circuit provides flexibility, the size of the circuit degrades its speed in comparison to the typical gate array circuit. Also, the size of the circuit diminishes the yield per wafer. The flexibility in specifying the gate array circuit also introduces additional problems The fuses are in close proximity to other fuses and components. With the close proximity and the large number of fuses, the probability that a fuse will not be blown properly increases and each circuit, which malfunctions because the fuses have been improperly blown, decreases the yield. Also, errors in programming the fuses cannot be detected until the device is completely programmed and tested to determine whether it performs the proper logical function.
The development of very large scale integrated memory arrays introduced a need for spare rows and columns of memory cells in addition to the primary memory array to assure reasonable yields. R. Smith et al. "Laser Programmable Redundancy and Yield Improvement in a 64K DRAM," IEEE J. of Solid-State Circuits, SC-16 No. 5, October, 1981. The spare rows and columns are interconnected to the memory array through laser programmable fusible links. If a defective row is detected in the primary memory array, appropriate fuses are blown to replace the defective row with one of the spare rows. Similarly, one of the spare columns of memory cells may be used to replace a defective column of memory cells in the primary memory array. Here the use of fusible links does not enhance the performance of the array. The redundant memory only enhances the yield of usable memory arrays.
Hence, in the prior art, arrays with fusible links which allow the user to configure the array into a desired circuit are well known. However, in each case the flexibility does not enhance the circuit performance and in most cases the flexibility significantly degrades the circuit performance with respect to speed. Also, with the exception of the DRAMs, the circuits with programmable links decrease the yield available from a wafer in comparison to similar circuits which do not contain such links.
In the prior art, laser programming of a silicon-based read only memory was disclosed by Cohen et al., "Encoding of Read Only Memory By Laser Vaporization", U.S. Pat. No. 3,740,523, issued June 19, 1973 and by J. North and W. Weick, "Laser Coding of Bipolar Read-Only Memories", IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 4, August 1976. In both of these disclosures, a read-only memory having a titanium-platinum-gold metallization and titanium platinum laser programmable links was disclosed. The link was formed by successively applying layers of titanium, platinum and gold on the silicon substrate and then etching the gold away in selected areas to form the programmable links Removable of the gold was necessary to avoid damage to the silicon substrate in the vaporization of the link.
Hence, the programmable link was not comprised of the same materials as the word or bit lines, and the link has more resistance than a link comprised of the same material as the word or bit lines. As with the electrically blown links, shown in FIG. 2b, the formation of the titanium-platinum link requires on additional processing step to etch away the metal overlying the link. If the etch step is not performed precisely, the fuse links will not be vaporized during the programming step.